Interfacing the Parallel Port
Version 4.2
Disclaimer :While every effort
has been made to make sure the information in this document is correct
the author can not be liable for any damages whatsoever for loss relating
to this document. Use this information at your own risk.
Table of Contents
Standard Parallel Port (SPP)
Introduction to Parallel Ports
Hardware Properties
Port Addresses
Software Registers (SPP)
Using the Parallel Port to Input 8 Bits
Bi-directional Ports
Using the Parallel Port's IRQ
Programming
Enhanced Parallel Port (EPP)
Enhanced Parallel Port
EPP Hardware Properties
The EPP Handshake
The EPP's Software Registers
Extended Capabilities Port (ECP)
Introduction to the Extended Capabilities Port
ECP Hardware Properties
The ECP Handshake
RLE - Run Length Encoding
ECP Software Registers
ECP's Extended Control Register (ECR)
ECP's Configuration Register A (cnfgA)
ECP's Configuration Register B (cnfgB)
Feedback
Feedback
Introduction to Parallel Ports
The Parallel Port is the most used port for interfacing home made projects.
This port will allow the input of up to 9 bits or the output of 12 bits
at any one given time. The port is composed of 4 control lines, 5 status
lines and 8 data lines. It's found commonly on the back of your PC as a
D-Type 25 Pin female connector. There may also be a D-Type 25 pin male
connector. This will be a serial RS-232 port and is a totally different
port.
For more information on Serial RS-232 Ports See http://www.senet.com.au/~cpeacock/serial1.htm
Before 1994 there were no set standards as to how the Parallel Port should
behave when connected to devices such as your humble printer, scanner,
CD-ROM drives etc. Some may use TTL (Transistor to Transistor Logic) while
others (more recent) may use CMOS (Complementary Metal Oxide Semiconductors)
chips in their drivers.
The IEEE 1284-1994 Standard. Defines 5 modes of operation. These are
1. Compatibility Mode.
2. Nibble Mode. (Protocol not Described in this Document)
3. Byte Mode. (Protocol not Described in this Document)
4. EPP Mode (Enhanced Parallel Port).
5. ECP Mode (Extended Capabilities Mode).
The aim was to design new drivers and devices which were compatible with
each other and also backwards compatible with the Standard Parallel Port
(SPP). Compatibility, Nibble & Byte modes use just the standard hardware
available on Parallel Port Cards while EPP & ECP modes require additional
hardware which can run at faster speeds, while still being downwards compatible
with the Standard Parallel Port.
Compatibility mode or "Centronics Mode" as it is commonly known,
can only send data in the forward direction at a typical speed of 50 kbytes
per second but can be as high as 150 kbytes a second. In order to receive
data, you must change the mode to either Nibble or Byte Mode. Nibble Mode
can input a nibble (4 bits) in the reverse direction. E.g. from device
to computer. Byte mode uses the Parallel's bi-directional feature (found
only on some cards) to input a byte (8 bits) of data in the reverse direction.
Extended and Enhanced parallel ports use additional hardware to generate
and manage handshaking. To output a byte to a printer (or anything in that
matter) using compatibility mode, the software must
1. Write the byte to the Data Port.
2. Check to see is the printer is busy. If the printer is busy, it will
not accept any data, thus any data which is written will be lost.
3. Take the Strobe (Pin 1) low. This tells the printer that there is
the correct data on the data lines. (Pins 2-9)
4. Put the strobe high again after waiting approximately 5 microseconds
after putting the strobe low. (Step 3)
This limits the speed at which the port can run at. The EPP & ECP ports
get around this by letting the hardware check to see if the printer is
busy and generate a strobe. This means only one I/O instruction need to
be performed, thus increasing the speed. These ports can output at around
1 Megabytes per second. The ECP port also has the advantage of using DMA
channels, thus data can be shifted around without using I/O instructions.
Hardware Properties
Below is a table of the "Pin Outs" of the D-Type 25 Pin
Connector and the Centronics 34 Pin Connector. The D-Type 25 pin connector
is the most common connector found on the Parallel Port of the computer, while
the Centronics Connector is commonly found on Printers. The IEEE 1284 standard
however specifies 3 different connectors for use with
the Parallel Port. The first one, 1284 Type A is the D-Type
25 connector found on the back of most computers. The 2nd is the 1284 Type B
which is the 36 pin Centronics Connector found on most printers.
IEEE 1284 Type C is also a 36 conductor connector, like the Centronics,
but smaller. This connector is claimed to have a better clip latch,
better electrical properties and is easier to assemble. It also contains
two more pins for signals which can be used to see whether the other device
connected, has power. 1284 Type C connectors are recommended for new designs,
so we can look forward on seeing these new connectors in the near future.
Pin No (D-Type 25) | Pin No (Centronics) | SPP Signal | Direction In/out | Register | Hardware Inverted |
1 |
1 |
nStrobe |
In/Out |
Control |
Yes |
2 |
2 |
Data 0 |
Out |
Data |
|
3 |
3 |
Data 1 |
Out |
Data |
|
4 |
4 |
Data 2 |
Out |
Data |
|
5 |
5 |
Data 3 |
Out |
Data |
|
6 |
6 |
Data 4 |
Out |
Data |
|
7 |
7 |
Data 5 |
Out |
Data |
|
8 |
8 |
Data 6 |
Out |
Data |
|
9 |
9 |
Data 7 |
Out |
Data |
|
10 |
10 |
nAck |
In |
Status |
|
11 |
11 |
Busy |
In |
Status |
Yes |
12 |
12 |
Paper-Out / Paper-End |
In |
Status |
|
13 |
13 |
Select |
In |
Status |
|
14 |
14 |
nAuto-Linefeed |
In/Out |
Control |
Yes |
15 |
32 |
nError / nFault |
In |
Status |
|
16 |
31 |
nInitialize |
In/Out |
Control |
|
17 |
36 |
nSelect-Printer / nSelect-In |
In/Out |
Control |
Yes |
18 - 25 |
19-30 |
Ground |
Gnd |
|
|
Table 1. Pin Assignments of the D-Type 25 pin Parallel Port
Connector.
The above table uses "n" in front of the signal name to denote that
the signal is active low. Eg nError. The printer has occurred an error when
this line is low. This line normally is high, should the printer be
functioning correctly. The "Hardware Inverted" means the signal
is inverted by the printer card's hardware. Such an example is the Busy line.
If +5v (Logic 1) was applied to this pin and the status register read, it
would return back a Logic 0 in the relevant position.
Port Addresses
The Printer/Parallel Port has three commonly used addresses. These are listed
in Table 2, below. The 3BCh base address is not
typically used today, but was once used when the Parallel Port was contained
on the video card. The address locations for LPT1 & LPT2 are typically
378h & 278h respectively. The lower case h denotes that it is in hexadecimal.
These addresses may change from machine to machine.
Address | Notes: |
3BCh - 3BFh | Used for Parallel Ports which were incorporated on to Video Cards - Doesn't support ECP addresses |
378h - 37Fh | Usual Address For LPT 1 |
278h - 27Fh | Usual Address For LPT 2 |
Table 2 Port Addresses
When the computer is first turned on, BIOS (Basic Input/Output System)
will determine the number of ports you have and assign device labels LPT1,
LPT2 & LPT3 to them. BIOS first looks at address 3BCh. If a
Parallel Port is found here, it is assigned as LPT1, then it searches at
location 378h. If a Parallel card is found there, it is assigned the next
free device label. This would be LPT1 if a card wasn't found at 3BCh or LPT2
if a card was found at 3BCh. The last port of call, is 278h and follows
the same procedure than the other two ports. Therefore it is possible to
have a LPT2 which is at 378h and not at the expected address 278h.
The assigned devices LPT1, LPT2 & LPT3 should not be a worry to people wishing
to interface devices to their PC's. Most of the time the base address is
used to interface the port rather than LPT1 etc. However should you want
to find the address of LPT1 or any of the Line
PrinTer Devices, you can use a lookup table provided by BIOS. When BIOS
assigns addresses to your printer devices, it stores the address at specific
locations in memory, so we can find them.
Start Address | Function |
0000:0408 | LPT1's Base Address |
0000:040A | LPT2's Base Address |
0000:040C | LPT3's Base Address |
0000:040E | LPT4's Base Address (Note 1) |
Table 3 - LPT Addresses in the BIOS Data Area;
Note 1 : Address 0000:040E in the BIOS Data Area may be used as the Extended
Bios Data Area in PS/2 and newer Bioses.
The above table, table 3, shows the address at which we can find the Printer
Port's addresses in the BIOS Data Area. Each address will take up 2 bytes. The
following sample program in C, shows how you can read these locations to obtain
the addresses of your printer ports.
#include <stdio.h>
#include <dos.h>
void main(void)
{
unsigned int far *ptraddr; /* Pointer to location of Port Addresses */
unsigned int address; /* Address of Port */
int a;
ptraddr=(unsigned int far *)0x00000408;
for (a = 0; a < 3; a++)
{
address = *ptraddr;
if (address == 0)
printf("No port found for LPT%d \n",a+1);
else
printf("Address assigned to LPT%d is %Xh\n",a+1,address);
*ptraddr++;
}
}
Software Registers - Standard Parallel Port (SPP)
Offset | Name | Read/Write | Bit No. | Properties |
Base + 0 | Data Port | Write (Note-1) | Bit 7 | Data 7 |
Bit 6 | Data 6 |
Bit 5 | Data 5 |
Bit 4 | Data 4 |
Bit 3 | Data 3 |
Bit 2 | Data 2 |
Bit 1 | Data 1 |
Bit 0 | Data 0 |
Base + 1 | Status Port | Read Only | Bit 7 | Busy |
Bit 6 | Ack |
Bit 5 | Paper Out |
Bit 4 | Select In |
Bit 3 | Error |
Bit 2 | IRQ (Not) |
Bit 1 | Reserved |
Bit 0 | Reserved |
Base + 2 | Control Port | Read/Write | Bit 7 | Unused |
Bit 6 | Unused |
Bit 5 | Enable Bi-Directional Port |
Bit 4 | Enable IRQ Via Ack Line |
Bit 3 | Select Printer |
Bit 2 | Initialize Printer (Reset) |
Bit 1 | Auto Linefeed |
Bit 0 | Strobe |
Table 3 Software Registers
Note 1 : If the Port is Bi-Directional then Read and Write Operations
can be performed on the Data Register.
The base address usually called the Data Port or Data Register, is simply
used for outputting data on the Parallel Port's data lines (Pins 2-9).
This port is normally a write only port. If you read from the port, you
should get the last byte sent. However if your port is bi-directional,
you can receive data on this address. See Bi-directional Ports for more
detail.
The Status Port/Register (base address + 1) is a read only port. Any data
written to this port will be ignored. The Status Port is made up of 5 input
lines (Pins 10,11,12,13 & 15), a IRQ status register and two reserved
bits. Please Note that Bit 7 (Busy) is a active low input. Eg If bit 7
happens to show a '0' this means that there is +5v at pin 11. Likewise
with Bit 2. (IRQ not) If this bit shows a '1' then an interrupt has not
occurred.
The Control Port (base address + 2) was intended as a write only port.
When a printer is attached to the Parallel Port, four "controls"
are used. These are Strobe, Auto Linefeed, Initialize and Select Printer,
all of which are inverted except Initialize.
The printer would not send a signal to initialize the computer, nor would
it tell the computer to use auto linefeed. However these four outputs can
also be used for inputs. If the computer has placed a pin high (eg +5v)
and your device wanted to take it low, you would effectively short out
the port, causing a conflict on the Bus. Therefore these lines are "open
collector " outputs (or Open Drain for CMOS devices). This means that
it has two states. A low state (0v) and a high impedance state (open circuit).
Normally the Printer Card will have Internal Pull-up resistors, but as
you would expect, not all will. Some may just have open collector outputs,
while others may even have normal totem pole outputs. In order to make
your device work correctly on as many Printer Ports as possible, you can
use an external resistor as well. Should you already have an internal resistor,
then it will act in Parallel with it, or if you have Totem pole outputs,
the resistor will act as a load.
An external 4.7k resistor can be used to pull the pin high. I wouldn't
use anything lower, just in case you do have an internal pull up resistor,
as the external resistor would act in parallel giving effectively, a lower
value pull up resistor. When in high impedance state the pin on the Parallel
Port is high (+5v). When the Parallel Port takes the pin low, 5 volts is
applied across the resistor giving zero volts at the output pin. This way
the 4 pins of the Control Port can be used for bi-directional data transfer.
However the Control Port must be set to xxxx0100 to be able to read data,
that is all pins to be +5v at the port so that you can pull it down to
GND (logic 0).
Bits 4 & 5 are internal controls. Bit four will enable the IRQ (See
Using the Parallel Ports IRQ) and Bit 5 will enable a bi-directional port
meaning that you can input 8 bits using (DATA0-7). This mode is only possible
if your card supports it. Bits 6 & 7 are reserved. Any writes to these
two bits will be ignored.
Bi-directional Ports
Bit 5 of the Control Port enables or disables the bi-directional function
of the Parallel Port. This is only available on true bi-directional ports.
When this bit is set to one, pins 2 to 9 go into high impedance state.
Once in this state you can enter data on these lines and retrieve it from
the Data Port (base address). Any data which is written to the Data Port
will be stored but will not be available at the data pins. To turn off
Bi-directional mode, set bit 5 of the Control Port to '0'.
However some ports don't behave in a similar fashion. (One of the problems
of not having standards before IEEE-1284) Other ports may require setting
bit 6 of the Control Port to enable Bi-directional mode and setting
of Bit 5 to dis-enable Bi-directional mode. Different manufacturers implement
their bi-directional ports in different ways. If you wish to use your Bi-directional
port to input data, test it with a logic probe or multimeter first to make
sure it is in bi-directional mode.
Using The Parallel Port to Input 8 Bits.
If your Parallel Port doesn't support bi-directional mode, don't despair.
You can input a maximum of 9 bits at any one given time. To do this you
can use the 5 input lines of the Status Port & the 4 input (open collector)
lines of the Control Port. Normally you only input either 4 bits (A Nibble)
or 8 bits (A Byte) at any one given time. Inputting a byte will leave one
line vacant. What I suggest is to leave pin 10 (Not-Acknowledgment) vacant,
so you can use it to generate an interrupt request. Note that xxxx0100
has to be written to the Control Port before you can read data from it.
Using the Parallel Port's IRQ
The Parallel Port's interrupt request is not used for printing under DOS
or Windows. Early versions of OS-2 used them, but don't anymore. Interrupts
are good when interfacing monitoring devices such as high temp alarms etc,
where you don't know when it is going to be activated. It's more efficient
to have an interrupt request rather than have the software poll the ports
regularly to see if something has changed. This is even more noticeable
if you are using you computer for other tasks, such as with a multitasking
operating system.
The down side to interrupts is that they are harder to program. It is beyond
the scope of this document to show you how it is done.
See Interfacing the PC : Using Interrupts
for more information.
The Parallel Port's
interrupt request is normally IRQ5 or IRQ7 but may be something else if
these are in use. It may also be possible that the interrupts are totally
disabled on the card, if the card was only used for printing. You must
program the Programmable Interrupt Controller (PIC) at address 020h to
respond to the interrupt you are using and then place an Interrupt Service
Routine (ISR) routine at the appropriate Interrupt Vector.
Programming
The source code contained here is for C / C++ compilers. To output a byte
is simple enough. You can use the outportb (Port
address, byte) instruction contained in the dos.h library. Each
of the 8 bits are packed into a byte which can be a numeral between 0 and
255 in decimal form. Each bit of a port is translated into a number shown
Below.
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
128 | 64 | 32 | 16 | 8 | 4 | 2 | 1 |
If we wanted to take Bit 0 of the Data Port high, we would use outportb(base
address,1); Likewise if we wanted to take bit 7 high, we would use
outportb(base address,128);
If we wanted to take high, two of more lines, the we must add the numbers
corresponding to the bits we want to take high. eg if we wanted Bit 0,
Bit 3, Bit 5 & Bit 6 high we would output outportb(base
address,169);
Bit 7 | Bit 5 | Bit 3 | Bit 0 | |
128 | +32 | +8 | +1 | =169 |
Below is an example assuming the port is at address 0x378 :
#include <dos.h> /* Contains the prototype for outportb & inportb */
void main(void);
{
outportb(0x378,1); /* Sets Bit 0 High (Pin 2) */
delay(1000);
outportb(0x378,2); /* Sets Bit 1 High (Pin 3) */
delay(1000);
outportb(0x378,5); /* Sets Bits 2 & 0 High (Pins 4 & 2) */
delay(1000);
outportb(0x378,129); /* Sets Bits 0 & 7 High (Pins 2 & 9) */
}
Receiving data from the port is practically the reverse process. Using
inportb(base address) we can get a byte of data from the port. This
will be a value representing the 8 bits. There are two (human) ways of
working out the bits which are set, you can divide the number by two taking
note of the remainder or given the number, subtract the most significant
bit's weight e.g. 128,64,32 etc. We will not proceed any further with these
methods as we don't want to decode it, we want the computer to do it.
Using C we can take advantage of the bitwise operators, in particular the
AND logic function. If we have a two input AND gate and fed in 1 &
1 into the inputs we hope to get 1 out (true), if we fed in anything else
we should get zero (False). If we use the instruction,
if (Byte & 128 ) printf("Bit 7\n");
the computer will look at the byte and 128 in a bitwise fashion. Lets say
the byte is equal to 134 in decimal then this will translate to 10000110.
The 128 will translate to 10000000. When an AND function is ran on the
last bit (Most Significant Bit) the output should be True, thus meaning
this bit is set. Looking at the above instruction, it would output to the
screen "BIT 7". If the instruction
if (byte & 64 ) printf("Bit 6\n");
was ran on the same byte then it would look at the
2nd to last bit. However this time the AND function would reply with a
0 (False), thus "Bit 6" would not be printed in the above case.
This can then be done for all the bits in the byte to find out if their
relevant pins are high or low.
The source code below shows an example of receiving (Inputting) data using
the above method.
#include <dos.h> /* Contains the prototype for inportb */
#include <stdio.h> /* Contains the prototype for printf */
void main(void)
{
int a;
a = inportb(0x378 + 1); /* Gets input from Status Port in byte form. */
printf(" %d \n",a); /* Prints byte value to screen in */
/* decimal form */
if (a & 128) printf("Bit 7 - Busy\n");
if (a & 64) printf("Bit 6 - Ack\n");
if (a & 32) printf("Bit 5 - Paper Out\n");
if (a & 16) printf("Bit 4 - Select In\n");
if (a & 8) printf("Bit 3 - Error\n");
if (a & 4) printf("Bit 2 - IRQ (NOT)\n");
if (a & 2) printf("Bit 1 - Reserved\n");
if (a & 1) printf("Bit 0 - Reserved\n");
}
This time we get our byte from Base + 1, which is the Status Port. Each
bit is AND'ed to determine whether it is set or not.
EPP - Enhanced Parallel Port
The Enhanced Parallel Port (EPP) is a rather recent addition to the modes
of which the Parallel Port can run. It was designed in a joint venture
between Intel, Xircom & Zenith Data Systems. EPP ports were first specified
in the EPP 1.7 standard, and then later included in the IEEE 1284 Standard
and often referred to as EPP 1.9. There are differences between the two
standards which may affect the operation of devices. They have a typical
transfer rate in the order of 500K to 2MBytes per second. This is achieved
by allowing the hardware contained in the port to generate handshaking,
strobing etc., rather that have the software do it.
EPP Hardware Properties
When using EPP mode, a different set of tasks are assigned to each line.
These are listed below in Table 4.
Pin | SPP Signal | EPP Signal | IN/OUT | Function |
1 | Strobe | Write | Out | A low on this line indicates a Write, High indicates a Read |
2-9 | Data 0-7 | Data 0-7 | In-Out | Data Bus. Bi-directional |
10 | Ack | Interrupt | In | Interrupt Line |
11 | Busy | Wait | In | Used for handshaking. A EPP cycle can be started when low, and finished when high. |
12 | Paper Out / End | Spare | In | Spare - Not Used in EPP Handshake |
13 | Select | Spare | In | Spare - Not Used in EPP Handshake |
14 | Auto Linefeed | Data Strobe | Out | When Low, indicates Data transfer |
15 | Error / Fault | Spare | In | Spare - Note used in EPP Handshake |
16 | Initialize | Reset | Out | Reset - Active Low |
17 | Select Printer | Address Strobe | Out | When low, indicates Address transfer |
18-25 | Ground | Ground | GND | Ground |
Table 4. Pin Assignments For Enhanced Parallel Port Connector.
Paper Out, Select and Error are not defined in the EPP handshake. These
lines can be utilized in any way by the user. The status of these lines
can be determined at anytime by viewing the SPP Status Register.
The EPP Handshake
In order to perform a valid exchange of data using EPP we must follow the
EPP handshake. As the hardware does all the work, this handshake only requires
to be used for your hardware and not for software as in SPP. To initiate
an EPP cycle your software needs to perform only one I/O operation to the
relevant EPP Register.
EPP Data Write Cycle
1. Program writes to EPP Data Register. (Base + 4)
2. Write is placed low. (Low indicates write operation)
3. Data is placed on Data Lines 0-7.
4. Data Strobe is asserted if Wait is Low (O.K. to start cycle)
5. Host waits for Acknowledgment by wait going high (O.K. to end cycle)
6. Data Strobe is De-asserted.
EPP Address Write Cycle
1. Program writes address to EPP's Address Register (Base + 3)
2. Write is placed low. (Low indicates write operation)
3. Address is placed on Data Lines 0-7.
4. Address Strobe is asserted if Wait is Low (O.K. to start cycle)
5. Host waits for Acknowledgment by wait going high (O.K. to end cycle)
6. Address Strobe is De-asserted.
Note
|
If implementing EPP 1.7 Handshake (Pre IEEE 1284) the Data and Address
Strobes can be asserted to start a cycle regardless of wait state. EPP 1.9 will
only start a cycle once wait is Low. Both EPP 1.7 and EPP 1.9 require the
wait to be high to finish a cycle.
|
The EPP's Software Registers.
Address | Port Name | Read/Write |
Base + 0 | Data Port (SPP) | Write |
Base + 1 | Status Port (SPP) | Read |
Base + 2 | Control Port (SPP) | Write |
Base + 3 | Address Port (EPP) | Read/Write |
Base + 4 | Data Port (EPP) | Read/Write |
Base + 5 | Undefined | - |
Base + 6 | Undefined | - |
Base + 7 | Undefined | - |
Table 5 EPP Registers
Above is a list of the EPP registers. As you can see, the first 3 addresses
are exactly the same than the Standard Parallel Port Register and behave
in exactly the same way. Therefore if you used a Enhanced Parallel Port,
you can output data to Base + 0 in exactly the same fashion than you would
if it was a Standard Parallel Port (SPP). If you were to connected a printer,
using compatibility mode then you would have to check to see if the port
is busy and then assert & de-assert the strobe using the Control and
Status Port.
If you wish to communicate with a EPP compatible device then all you have
to do, is place any data you wish to send in the EPP Data Register at Base
+ 4 and the card will generate all the necessary handshaking required.
Likewise if you wish to send an address to your device, then you use the
EPP Address Register at offset +3.
Both the EPP Address Register and the EPP Data Register are read / write,
thus to read data from your device, you can use the same Registers. However
the EPP Printer Card has to initiate a read Cycle as both the Data Strobe
and Address Strobe are outputs. Your device can signal a read request via
the use of the interrupt.
Introduction to the Extended Capabilities Port
The Extended Capabilities Mode was designed by Hewlett Packard and Microsoft
to be implemented as the Extended Capabilities Port Protocol and ISA
Interface Standard. This protocol uses additional hardware to generate
handshaking signals etc just like the EPP mode, thus runs at very much
the same speed than the EPP mode. This mode, however may work better under
Windows as it can use DMA channels to move it's data about. It also uses
a FIFO buffer for the sending and/or receiving of data.
Another feature of ECP is a real time data compression. It uses Run Length
Encoding (RLE) to achieve data compression ratio's up to 64:1. This comes
is useful with devices such as Scanners and Printers where a good part
of the data is long strings which are repetitive.
The Extended Capabilities Port supports a method of channel addressing.
This is not intended to be used to daisy chain devices up but rather to
address multiple devices within one device. Such an example is many fax
machines on the market today which may contain a Parallel Port to interface
it to your computer. The fax machine can be split up into separate devices
such as the scanner, modem/Fax and printer, where each part can be addresses
separately, even if the other devices cannot accept data due to full buffers.
ECP Hardware Properties
While Extended Capabilities Printer Ports use exactly the same D25 connector
as your SPP, ECP assigns different tasks to each of the pins, just like
EPP. This means that there is also a different handshake method when using
a ECP interface.
The ECP is backwards compatible to the SPP and EPP. When operating in SPP
mode, the individual lines operate in exactly the same fashion than the
SPP and thus are labeled Strobe, Auto Linefeed, Init, Busy etc. When operating
in EPP mode, the pins function according to the method described in the
EPP protocol and have a different method of Handshaking. When the port
is operating in ECP mode, then the following labels are assigned to each
pin.
Pin | SPP Signal | ECP Signal | IN/OUT | Function |
1 | Strobe | HostCLK | Out | A low on this line indicates, that there is valid data at the host. When this pin is de-asserted, the +ve clock edge should be used to shift the data into the device. |
2-9 | Data 0-7 | Data 0-7 | In/Out | Data Bus. Bi-directional |
10 | Ack | PeriphCLK | In | A low on this line indicates, that there is valid data at the Device. When this pin is de-asserted, the +ve clock edge should be used to shift the data into the Host. |
11 | Busy | PeriphAck | In | When in reverse direction a HIGH indicates Data, while a LOW indicates a Command Cycle. In forward direction, functions as PeriphAck. |
12 | Paper Out / End | AckReverse | In | When Low, Device acknowledges Reverse Request. |
13 | Select | X-Flag | In | Extensibility Flag |
14 | Auto Linefeed | Host Ack | Out | When in forward direction a HIGH indicates Data, while a LOW indicates a Command Cycle. In reverse direction, functions as HostAck. |
15 | Error / Fault | PeriphRequest | In | A LOW set by the device indicates reverse data is available |
16 | Initialize | ReverseRequest | Out | A LOW indicates data is in reverse direction |
17 | Select Printer | 1284 Active | Out | A HIGH indicates Host is in 1284 Transfer Mode |
18-25 | Ground | Ground | GND | Ground |
Table 6. Pin Assignments For Extended Capabilities Parallel Port Connector.
The HostAck and PeriphAck lines indicate whether the signals on the data
line are data or a command. If these lines are high then data is placed
on the data lines (Pins 2-7). If a command cycle is taking place then the
appropriate line will be low, ie if the host is sending a command, then
HostAck will be low or if the device/peripheral is sending a command the
PeriphAck line will be low.
A command cycle can be one of two things, either a RLE count or an address.
This is determined by the bit 7 (MSB) of the data lines, ie Pin 9. If bit
7 is a 0, then the rest of the data (bits 0-6) is a run length count which
is used with the data compression scheme. However if bit 7 is a 1, then
the data present on bits 0 to 6 is a channel address. With one bit missing
this can only be a value from 0 to 127(DEC).
The ECP Handshake
The ECP handshake is different to the SPP handshake. The most obvious difference
is that ECP has the ability at anytime to transmit data in any direction,
thus additional signaling is required. Below is the ECP handshake for both
the Forward and Reverse Directions.
Forward Direction (Data from Host is sent to Device/Peripheral.)
1. Data is placed on Data lines by Host.
2. Host then indicates a Data Cycle Or Command Cycle via HostAck.
3. Host indicates valid data by asserting HostClk low.
4. Device/Peripheral Sends its Acknowledgment of Valid Data via PeriphAck.
5. Host sets HostClk High. +ve edge used to shift data into the Peripheral's registers.
6. Device/Peripheral Sends it's Acknowledgment of the Byte via PeriphAck.
Reverse Direction (Data from Device/Peripheral is sent to Host.)
1. Host sets ReverseRequest Low to request a reverse channel.
2. Device/Peripheral Acknowledges Reverse Channel Request via a LOW on AckReverse.
3. Data is placed on data lines by Device/Peripheral.
4. Data or Command cycle is then set by Device/Peripheral via PeriphAck.
5. Valid Data is indicated by the Device/Peripheral setting PeriphClk low.
6. Host Sends its Acknowledgment of Valid Data via PeriphAck.
7. Device/Peripheral sets PeriphClk High. +ve edge used to shift data into the Host's registers.
8. Host Sends it's Acknowledgment of the Byte via HostAck.
If we look back at the SPP Handshake you will realize it only has 4 steps,
1. Write the byte to the Data Port.
2. Check to see is the printer is busy. If the printer is busy, it will
not accept any data, thus any data which is written will be lost.
3. Take the Strobe (Pin 1) low. This tells the printer that there is
the correct data on the data lines. (Pins 2-9)
4. Put the strobe high again after waiting approximately 5 microseconds
after putting the strobe low. (Step 3)
and that the ECP handshake has many more steps. This would suggest that
ECP would be slower that SPP. However this is not the case as all of these
steps above are controlled by the hardware on your I/O control. If this
handshake was implemented via software control then it would be a lot slower
that it's SPP counterpart.
RLE - Run Length Encoding
As briefly discussed earlier, the ECP Protocol includes a Simple Compression
Scheme called Run Length Encoding. It can support a maximum compression
ratio of 64:1 and works by sending repetitive single bytes as a run count
and one copy of the byte. The run count determines how many times the following
byte is to be repeated.
For example, if a string of 25 'A's were to be sent, then a run count byte
equal to 24 would be sent first, followed by the byte 'A'. The receiving
peripheral on receipt of the Run Length Count, would expand (Repeat) the
next byte a number of times determined via the run count.
The Run Length Byte has to be distinguished from other bytes in the Data
Path. It is sent as a Command to the ECP's Address FIFO Port. Bytes sent
to this register can be of two things, a Run Length Count or an Address.
These are distinguished by the MSB, Bit 7. If Bit 7 is Set (1), then the
other 7 bits, bits 0 to 6 is a channel address. If Bit 7 is Reset (0),
then the lower 7 bits is a run length count. By using the MSB, this limits
channel Addresses and Run Length Counts to 7 Bits (0 - 127).
ECP Software Registers
The table below shows the registers of the Extended Capabilities Port.
The first 3 registers are exactly the same than with the Standard Parallel
Port registers. Note should be taken, however, of the Enable Bi-Directional
Port bit (bit 5 of the Control Port.) This bit reflects the direction that
the ECP port is currently in, and will effect the FIFO Full and FIFO Empty
bits of the ECR Register, which will be explained later.
Address | Port Name | Read/Write |
Base + 0 | Data Port (SPP) | Write |
ECP Address FIFO (ECP MODE) | Read/Write |
Base + 1 | Status Port (All Modes) | Read/Write |
Base + 2 | Control Port (All Modes) | Read/Write |
Base + 400h | Data FIFO (Parallel Port FIFO Mode) | Read/Write |
Data FIFO (ECP Mode) | Read/Write
Test FIFO (Test Mode) | Read/Write |
Configuration Register A (Configuration Mode) | Read/Write |
Base + 401h | Configuration Register B (Configuration Mode) | Read/Write |
Base + 402h | Extended Control Register (Used by all modes) | Read/Write |
Table 7 ECP Registers
ECP's Extended Control Register (ECR)
The most important register with a Extended Capabilities Parallel Port
is the Extended Control Register (ECR) thus we will target it's operation
first. This register sets up the mode in which the ECP will run, plus gives
status of the ECP's FIFO among other things. You will find the contents
of this register below, in more detail.
Bit | Function |
7:5 | Selects Current Mode of Operation |
000 | Standard Mode |
001 | Byte Mode |
010 | Parallel Port FIFO Mode |
011 | ECP FIFO Mode |
100 | EPP Mode |
101 | Reserved |
110 | FIFO Test Mode |
111 | Configuration Mode |
4 | ECP Interrupt Bit |
3 | DMA Enable Bit |
2 | ECP Service Bit |
1 | FIFO Full |
0 | FIFO Empty |
Table 8 ECR - Extended Control Register
The three MSB of the Extended Control Register selects the mode of operation.
There are 7 possible modes of operation, but not all ports will support
all modes. The EPP mode is one such example, not being available on some
ports. Below is a table of Modes of Operation.
Modes of Operation
|
Standard Mode | Selecting this mode will cause the ECP port to behave as a Standard Parallel Port, without Bi-directional functionality. |
Byte Mode / PS/2 Mode | Behaves as a SPP in Bi-directional (Reverse) mode. |
Parallel Port FIFO Mode | In this mode, any data written to the Data FIFO will be sent to the peripheral using the SPP Handshake. The hardware will generate the handshaking required. Useful with non-ECP devices such as Printers. You can have some of the features of ECP like FIFO buffers and hardware generation of handshaking but with the existing SPP handshake instead of the ECP Handshake. |
ECP FIFO Mode | Standard Mode for ECP Use. This mode uses the ECP Handshake, already described. |
EPP Mode/Reserved | On some chipsets, this mode will enable EPP to be used. While on others, this mode is still reserved. |
Reserved | Currently Reserved |
FIFO Test Mode |
While in this mode, any data written to the Test FIFO Register will
be placed into the FIFO and any data read from the Test FIFO register will
be read from the FIFO buffer. The FIFO Full/Empty Status Bits will reflect
their true value, thus FIFO depth, among other things can be determined
in this mode.
|
Configuration Mode | In this mode, the two configuration registers, cnfgA & cnfgB become available at their designated Register Addresses. |
|
As outlined above, when the port is set to operate in Standard Mode,
it will behave just like a Standard Parallel Port (SPP) with no bi-directional
data transfer. If you require bi-directional transfer, then set the mode
to Byte Mode. The Parallel Port FIFO mode and ECP FIFO mode both use hardware
to generate the necessary handshaking signals. The only difference between
each mode is that The Parallel Port FIFO Mode uses SPP handshaking, thus
can be used with your SPP printer. ECP FIFO mode uses ECP handshaking.
The FIFO test mode can be used to test the capacity of the FIFO Buffers
as well as to make sure they function correctly. When in FIFO test mode,
any byte which is written to the TEST FIFO (Base + 400h) is placed into
the FIFO buffer and any byte which is read from this register is taken
from the FIFO Buffer. You can use this along with the FIFO Full and FIFO
Empty bits of the Extended Control Register to determine the capacity of
the FIFO Buffer. This should normally be about 16 Bytes deep.
The other Bits of the ECR also play an important role in the operation
of the ECP Port. The ECP Interrupt Bit, (Bit 4) enables the use of Interrupts,
while the DMA Enable Bit (Bit 3) enables the use of Direct Memory Access.
The ECP Service Bit (Bit 2) shows if an interrupt request has been initiated.
If so, this bit will be set. Resetting this bit is different with different
chips. Some require you to Reset the Bit, E.g. Write a Zero to it. Others
will reset once the Register has been read.
The FIFO Full (Bit 1) and FIFO Empty (Bit 0) show the status of the FIFO Buffer.
These bits are direction dependent, thus note should be taken of the Control
Register's Bit 5. If bit 0 (FIFO Empty) is set, then the FIFO buffer is
completely empty. If Bit 1 is set then the FIFO buffer is Full. Thus, if
neither bit 0 or 1 is set, then there is data in FIFO, but is not yet full.
These bits can be used in FIFO Test Mode, to determine the capacity of
the FIFO Buffer.
ECP's Configuration Register A (cnfgA)
Configuration Register A is one of two configuration registers which the
ECP Port has. These Configuration Registers are only accessible when the
ECP Port is in Configuration Mode. (See Extended Control Register) CnfgA
can be accessed at Base + 400h.
Bit | Function |
7 | 1 | Interrupts are level triggered |
0 | Interrupts are edge triggered (Pulses) |
6:4 | 00h | Accepts Max. 16 Bit wide words |
01h | Accepts Max. 8 Bit wide words |
02h | Accepts Max. 32 Bit wide words |
03h:07h | Reserved for future expansion |
3 | Reserved |
2 | Host Recovery : Pipeline/Transmitter Byte included in FIFO? |
0 | In forward direction, the 1 byte in the transmitter pipeline doesn't affect FIFO Full. |
1 | In forward direction, the 1 byte in the transmitter pipeline is include as part of FIFO Full. |
1:0 | Host Recovery : Unsent byte(s) left in FIFO |
00 | Complete Pword |
01 | 1 Valid Byte |
10 | 2 Valid Bytes |
11 | 3 Valid Bytes |
Table 9 ECR - Configuration Register A
Configuration Register A can be read to find out a little more about the
ECP Port. The MSB, shows if the card generates level interrupts or edge triggered interrupts. This will depend upon the
type of bus your card is using. Bits 4 to 6, show the buses width within
the card. Some cards only have a 8 bit data path, while others may have
a 32 or 16 bit width. To get maximum efficiency from your card, the software
can read the status of these bits to determine the Maximum Word Size to
output to the port.
The 3 LSB's are used for Host Recovery. In order to recover from an error,
the software must know how many bytes were sent, by determining if there
are any bytes left in the FIFO. Some implementations may include the byte
sitting in the transmitter register, waiting to be sent as part of the
FIFO's Full Status, while others may not. Bit 2 determines weather or not
this is the case.
The other problem is that the Parallel Ports output is only 8 bits wide,
and that you many be using 16 bit or 32 bit I/O Instructions. If this is
the case, then part of your Port Word (Word you sent to port) may be sent.
Therefore Bits 0 and 1 give an indication of the number of valid bytes
still left in the FIFO, so that you can retransmit these.
ECP's Configuration Register B (cnfgB)
Configuration Register B, like Configuration Register A is only available
when the ECP Port is in Configuration Mode. When in this mode, cnfgB resides
at Base + 401h. Below is the make-up of the cnfgB Register.
Bit(s) | Function |
7 | 1 | Compress outgoing Data Using RLE |
0 | Do Not compress Data |
6 | Interrupt Status - Shows the Current Status of the IRQ Pin |
5:3 | Selects or Displays Status of Interrupt Request Line. |
000 | Interrupt Selected Via Jumper |
001 | IRQ 7 |
010 | IRQ 9 |
011 | IRQ 10 |
100 | IRQ 11 |
101 | IRQ 14 |
110 | IRQ 15 |
111 | IRQ 5 |
2:0 | Selects or Displays Status of the DMA Channel the Printer Card Uses |
000 | Uses a Jumpered 8 Bit DMA Channel |
001 | DMA Channel 1 |
010 | DMA Channel 2 |
011 | DMA Channel 3 |
100 | Uses a Jumpered 16 Bit DMA Channel |
101 | DMA Channel 5 |
110 | DMA Channel 6 |
111 | DMA Channel 7 |
Table 10 - Configuration B Register
The Configuration Register B (cnfgB) can be a combination of read/write
access. Some ports may be software configurable, where you can set the
IRQ and DMA resources from the register. Others may be set via BIOS or
by using jumpers on the Card, thus are read only.
Bit 7 of the cnfgB Register selects whether to compress outgoing data using
RLE (Run Length Encoding.) When Set, the host will compress the data before
sending. When reset, data will be sent to the peripheral raw (Uncompressed).
Bit 6 returns the status of the IRQ pin. This can be used to diagnose conflicts
as it will not only reflect the status of the Parallel Ports IRQ, but and
other device using this IRQ.
Bits 5 to 3 give status of about the Port's IRQ assignment. Likewise for
bits 2 to 0 which give status of DMA Channel assignment. As mentioned above
these fields may be read/write. The disappearing species of Parallel Cards
which have Jumpers may simply show it's resources as "Jumpered"
or it may show the correct Line Numbers. However these of course will be
read only.
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